1. Technical Field
Example embodiments relate to an overlay mark for measuring overlay accuracy of circuit patterns sequentially stacked on a semiconductor substrate and a method of forming the same.
2. Description of the Related Art
A semiconductor device may be manufactured by repeatedly forming thin layers having electrical circuit patterns on a semiconductor substrate (e.g., a silicon wafer). The thin layers may be formed by various processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other suitable processes. The circuit patterns may be formed by a photolithography process.
Overlay accuracy of the thin layers may be measured using an overlay mark formed on the thin layers. The overlay mark may include a lower overlay pattern formed on a lower layer and an upper overlay pattern formed on an upper layer. The overlay mark may have a box-in-box shape. Overlay accuracy may be determined by measuring the alignment of the lower overlay pattern and the upper overlay pattern. An alignment correction value of a wafer and a photo mask or a reticle in a photolithography process may be adjusted based on the overlay accuracy. As semiconductor devices may become more integrated, the size of patterns on the semiconductor substrate may decrease. Consequently, accurate measurement of the overlay in a photolithography process may become more important.
FIG. 1 is a scanning electron microscope (SEM) image showing a conventional overlay mark. FIG. 2 is a cross-sectional view illustrating the conventional overlay mark in FIG. 1. Referring to FIGS. 1 and 2, first photoresist patterns 12 may be formed on a cell region A of a semiconductor substrate, and second photoresist patterns 14 may be formed on a scribe lane region B of the semiconductor substrate. To form circuit patterns in the cell region A, the first photoresist patterns 12 may be arranged more densely in the cell region A. In contrast, to form an overlay mark 16 in the scribe lane region B, the second photoresist patterns 14 may be arranged more sparsely in the scribe lane region B compared to the first photoresist patterns 12 in the cell region A. The second photoresist patterns 14 may be wider than the first photoresist patterns 12.
In an etching process using a photoresist pattern as a mask, the etching speed in a larger etching area may be greater than the etching speed in a smaller etching area depending on etching conditions. For example, a phenomenon referred to as “reverse reactive ion etching (RIE) lag” may be caused by the use of gases (e.g., hexafluorethane (C2F6), perfluoropropane (C3F8), octafluorocyclobutane (C4F8)) that generate larger amounts of polymer during the etching process.
When a layer 10 is etched using the first photoresist pattern 12 and the second photoresist pattern 14 as an etching mask, the etching conditions may be determined in accordance with the width of the first photoresist pattern 12 in the cell region A. However, an opening formed using the second photoresist pattern 14 may have a width greater than an opening formed using the first photoresist pattern 12. Consequently, polymer may accumulate on an exposed portion of the layer 10 via the second photoresist pattern 14 during the etching process. The accumulated polymer may interfere with the etching process such that process failures (e.g., etching stop) may occur. The etching failure may obstruct formation of the overlay mark 16. Furthermore, a pattern 18 may be formed in the opening (e.g., overlay mark 16). As a result, the pattern 18 in the overlay mark 16 may render it more difficult to identify the overlay mark 16 when measuring overlay accuracy. Accordingly, the reliability of the overlay accuracy measurement may be lowered.